System Clock Jitter Correction

ABSTRACT

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

RELATED APPLICATIONS

This application is a Continuation of an application entitled, SYSTEMCLOCK JITTER CORRECTION, invented by Mikko Waltari et al., Ser. No.14/507,563, filed Oct. 6, 2014;

which is a Continuation of an application entitled, FREQUENCY MULTIPLIERJITTER CORRECTION, invented by Mikko Waltari, Ser. No. 14/503,656, filedOct. 1, 2014;

which is a Continuation of an application entitled, SYSTEM AND METHODFOR FREQUENCY MULTIPLIER JITTER CORRECTION, invented by Mikko Waltari,Ser. No. 14/081,568, filed Nov. 15, 2013, issued as U.S. Pat. No.8,878,577 on Nov. 4, 2014;

which is a Continuation-in-Part of an application entitled,TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER FOR SIGNALS IN ANY NYQUISTZONE, invented by Mikko Waltari, Ser. No. 13/603,495, filed Sep. 5,2012, issued as U.S. Pat. No. 8,654,000, on Feb. 18, 2014. All theseapplications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to analog-to-digital signal conversionand, more particularly, to a system and method for correcting phaseerrors in a synthesized frequency multiplier clock signal.

2. Description of the Related Art

FIG. 1 depicts a phase-locked loop (PLL) consisting of a phase frequencydetector (PFD), a voltage controlled oscillator (VCO), a charge pump(CP), and a loop filter placed into the forward path of a negativefeedback closed loop configuration (prior art). The charge pump convertsthe pulse width modulated output voltage of the PFD into current pulses.The amplitude of the current is often made to track some static oralmost static parameter such as the manufacturing process, temperature,and supply voltage. It can also be varied with the output frequency ofthe PLL. The VCO runs at the desired output clock frequency, or somemultiple of it. Due to fundamental limitations the VCO itself is notinherently accurate or stable. To obtain a stable and accurate outputfrequency the VCO is enclosed in a feedback loop, where the outputfrequency is divided down and compared to a much lower frequencyreference clock typically produced by a crystal oscillator. The looplocks the divided down VCO output to the reference frequency, resultinga stable output frequency that is an integer (N) multiple of thereference frequency.

A linear or harmonic type VCO includes a varactor whose capacitance isresponsive to the input control voltage, and is used to change thecapacitance in an inductor-capacitor (LC) tank circuit or crystalresonator. A delay-based ring VCO operates using gain stages connectedin a ring, with the output frequency being a function of the delay ineach of stages.

Another type of frequency multiplier is the digital PLL, which operatesin much the same manner as a PLL, except that the VCO is replaced by adigitally controlled oscillator (DCO) that runs at the required clockfrequency, or some multiple, in response to digital input controlsignals supplied by a digital phase frequency detector. Still anotherfrequency multiplier is a delay-locked loop (DLL), which has acontrolled delay line that is voltage or digitally controlled. The DLLgenerates a plurality of phase shifted versions of the reference clockthat are combined to produce a new clock signal that is a multiple ofthe reference frequency.

The most common type of reference source is a crystal oscillator, whichrelies upon the inherent stability of quartz crystal to provide areference frequency that remains constant within a few parts permillion. Microelectromechanical system (MEMS) resonators are smallelectromechanical structures that vibrate at high frequencies. Forfrequency and timing references, MEMS resonators are attached tosustaining amplifiers, to drive them in continuous motion and produceoutput reference signals. MEMS oscillators can be fabricated asmulti-pin integrated circuits (ICs) to supply multiple signal phases.

The sampling clock for an analog-to-digital converter (ADC) is oftengenerated using a PLL. Typically, the jitter of the sampling clock isdominated by the close-in phase noise of the PLL, especially when a ringoscillator type VCO is used. The clock jitter is one of the mainlimitations to the ADC signal-to-noise ratio (SNR) when sampling ahigh-frequency input signal. A crystal oscillator can provide areference signal with a minimum of phase noise, but the availablefrequencies are too low for many applications.

One limitation, especially when the ratio of the output frequency to thereference frequency is large, is that the VCO must run many cyclesbetween the generation of any correction information from phasecomparisons with the reference signal, which occurs only once in thereference period. Between the feedback pulses (control signals to theVCO) at the rate of the reference frequency, the output phase can driftdue to device noise or some external disturbance. To keep the feedbackloop stable, the amount of correction that can be applied at a singlereference period is also limited by the bandwidth of the loop-filter,which further delays the phase error correction. As a result, there is alimit to how much of the VCO phase noise the feedback loop can correct.

It would be advantageous if a method existed that provided animprovement in the phase noise correction possible in a system usingphase-locked system clock.

SUMMARY OF THE INVENTION

Disclosed herein are a system and method to estimate the instantaneousphase error of a frequency multiplier, such as a phase-locked loop (PLL)output clock, and use this estimate to digitally suppress the resultantsampling error from an analog-to-digital (ADC) output. Phase errorcorrections are made by comparing the frequency multiplier output toreference signal at multiple instances within a reference signal period.These phase error corrections are applied in a feedforward manner to thesampled ADC output.

Accordingly, a method is provided for frequency multiplication jittercorrection. The method accepts an analog reference signal having acontinuous amplitude, continuous phase information, and a firstfrequency. Using the analog reference signal, a system clock signal isderived having a second frequency, greater than the first frequency. APLL using a voltage controlled oscillator (VCO) is one example of afrequency multiplier. The method samples the continuous amplitude (e.g.,sine wave) of the analog reference signal using the system clock signaland converts the sampled analog reference signal into a digitizedreference signal. In response to comparing the digitized referencesignal to an ideal digitized reference signal, a phase error correctionis derived for the system clock. If the amplitude of an analog datasignal is sampled at the first instance of time with a system clocksignal and converted into a digitized data signal, then the phase errorcorrection derived at the first instance of time can be applied to thedigitized data signal.

The ideal digitized reference signal is created by collecting samples ofthe digitized reference signal over a plurality of digitized referencesignal periods, at a plurality period reference points, and low-passfiltering the collected samples of the digitized reference signal periodreference point samples. More explicitly, the phase error correction isfound by subtracting the ideal digitized reference signal from thedigitized reference signal to supply a difference signal. Then, thephase error correction is derived by finding an inverse of a derivativeof the ideal digitized reference signal, and multiplying the differencesignal by the inverse of the derivative.

When the analog data signal is inside the first Nyquist zone, the phaseerror correction is applied to a delayed digitized data signal byfinding the derivative of the delayed digitized data signal, andmultiplying the derivative of the delayed digitized data signal by thephase error correction to supply a product. Then, the product issubtracted from the delayed digitized data signal. When the analog datasignal is outside of the first Nyquist zone, the derivative of delayeddigitized data signal creates a first result and a Hilberttransformation is performed on the delayed digitized data signal tosupply a second result. The second result is multiplied by a Nyquistzone-dependent constant to supply a third result and summed with thefirst result to supply a product that is subtracted from the delayeddigitized data signal.

In other aspects, the phase error correction can be used to control aprogrammable delay in the system clock signal, so as to create a phasecorrected system clock signal. As another alternative, the phase errorcorrection can be supplied to the frequency multiplier and used as acontrol signal to modify the phase of the system clock oscillatorsupplying the system clock signal.

Additional details of that above-described method and a system forfrequency multiplier jitter correction are provided below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a phase-locked loop (PLL) consisting of a phase frequencydetector, a voltage controlled oscillator (VCO), a charge pump (CP), anda loop filter placed into the forward path of a negative feedback closedloop configuration (prior art).

FIG. 2 is a schematic block diagram of a system for frequency multiplierjitter correction.

FIG. 3 is a schematic block diagram depicting details of the jitterestimation module.

FIG. 4 is a schematic block diagram of the system of FIG. 2 featuringadditional details.

FIG. 5 is a schematic block diagram depicting a variation of the systemdescribed by FIG. 4.

FIG. 6 is a schematic block diagram depicting an exemplary frequencysource with analog reference frequency slope control.

FIG. 7 is a block diagram depicting the jitter correction module ingreater detail.

FIG. 8 is a schematic block diagram of the derivative module of FIG. 7in the case where the analog data signal is outside of the first Nyquistzone, with a frequency of greater than f_(s)/2.

FIG. 9 is a schematic block diagram of a computer that may be used toenable all or some portions of ADCs, jitter estimation module, andjitter correction module.

FIG. 10 depicts the system of FIG. 4 from a slightly differentperspective.

FIGS. 11 and 12 are, respectively, an exemplary block diagram of thejitter estimation module, and associated waveforms.

FIG. 13 depicts an example of the jitter correction module.

FIG. 14 is a schematic block diagram depicting a variation of the phaseerror correction system.

FIG. 15 is a schematic block diagram depicting an exemplary jitterdetection and correction module, such as might be used in the system ofFIG. 14.

FIGS. 16A and 16B are flowcharts illustrating a method for frequencymultiplication jitter correction.

FIGS. 17A and 17B are schematic block diagrams of a system forcorrecting the phase error in the system clock signal.

FIG. 18 is a schematic block diagram depicting an alternate system forcorrecting system clock signal phase error.

FIGS. 19A and 19B are schematic block diagrams depicting two examples ofthe system of FIG. 18 in greater detail.

DETAILED DESCRIPTION

FIG. 2 is a schematic block diagram of a system for frequency multiplierjitter correction. The system 200 comprises a frequency multiplier 202with an input on line 204 to accept an analog reference signal having afirst frequency, and an output on line 206 to supply a system clocksignal having a second frequency, greater than the first frequency. Forexample, the frequency multiplier 202 may be a phase-locked loop (PLL)or a delay-locked loop (DLL). As used herein, an analog signal iscontinuous in amplitude and phase, while a digital or digitized signalis quantized in amplitude and phase. The system clock signal, especiallywhen used as an analog sampling clock, is quantized (using two levels)in amplitude, but continuous in phase.

A first analog-to-digital converter (ADC) 208 has a signal input on line204 to accept the analog reference signal, a clock input on line 206 toaccept the system clock signal, and an output on line 212 to supply adigitized reference signal in response to sampling the amplitude of theanalog reference signal using the system clock signal. The analog signalamplitude being sampled may be either a current or voltage amplitude. Ajitter estimation module 214 has an input on line 212 to accept thedigitized reference signal. The jitter estimation module 214 comparesthe digitized reference signal to an ideal digitized reference signal.In response to the comparing, the jitter estimation module 214determines a phase error in the system clock signal and supplies a phaseerror correction on line 216.

FIG. 3 is a schematic block diagram depicting details of the jitterestimation module. In one aspect, the jitter estimation module 214comprises a low-pass filter bank 300 with an input on line 212 to acceptthe digitized reference signal. The low-pass filter bank 300 samples thedigitized reference signal over a plurality of digitized referencesignal periods at a plurality of period reference points. The low-passfilter bank 300 has outputs on lines 304-0 through 304-n to supply theideal digitized reference signal, where n is an integer greater thanone, but otherwise not limited to any particular value. For example, nmay be equal to 3 and the period reference points may be the amplitudeof the digitized reference signal at the phases of 0, 90, 180, and 270degrees, averaged over may cycles of the digitized reference signal. Amore explicit implementation of the low-pass filter bank 300 is providedbelow. A variety of low-pass filtering algorithms are known in the artmay be used to enable the low-pass filter bank 300. Once such algorithmis the moving average filter.

FIG. 4 is a schematic block diagram of the system of FIG. 2 featuringadditional details. In this aspect, the jitter estimation module 214determines the phase error in the system clock at a first instance oftime and supplies the phase error correction on line 216. The system 200further comprises a jitter correction module 400 having a first input toaccept a digitized data signal on line 402 and a second input to acceptthe phase error correction on line 216. A second ADC 404 has a signalinput on line 406 to accept an analog data signal at the first instanceof time, and a clock input to accept the system clock signal on line206. The second ADC 404 has an output on line 402 to supply thedigitized data signal in response to sampling the amplitude of theanalog data signal with the system clock signal. Again, the amplitudebeing sampled may be a current or voltage amplitude. Further, the secondADC 404 need not necessarily be the same type of ADC as the first ADC208. The jitter correction module 400 applies the phase error correctionto the digitized data signal and supplies a phase corrected digitizeddata signal at an output on line 408.

Some of the types of ADCs from which the first ADC 208 and second ADC400 may be selected include direct-conversion (flash), successiveapproximation, ramp-compare, integrating (dual or multi-slope),pipelined, oversampling, and time-interleaved ADCs. Other types of ADCsmay exist, and the system 200 is not limited to any particular type ortypes of ADCs.

The jitter estimation module 214 supplies the phase error correction online 216 within a duration of time no greater than a first processingtime. The jitter correction module 400 applies the phase errorcorrection within a duration of time no greater than a second processingtime. Therefore, the jitter correction module 400 may further comprise adelay 410 having an input on line 402 to accept the digitized datasignal and an output on line 412 supply a delayed digitized data signal,delayed a first duration of time equal to the sum of the first andsecond processing times. Then, the jitter correction module 400 appliesthe phase error correction to the delayed digitized data signal.

FIG. 5 is a schematic block diagram depicting a variation of the systemdescribed by FIG. 4. In this aspect, the frequency multiplier 200, inaddition to supplying the system clock signal with the second frequencyon line 206 a, supplies a system clock signal on line 206 b having athird frequency, different than the first and second frequencies,derived from the analog reference signal on line 204. The first ADC 208samples the analog reference signal on line 204 with the system clocksignal having the second frequency, but the second ADC 404 samples theanalog data signal on line 406 with the system clock having the thirdfrequency.

FIG. 6 is a schematic block diagram depicting an exemplary frequencysource with analog reference signal slope control. In this aspect afrequency source 600 is shown with a first output on line 602 to supplya first signal having the first frequency, and a second output on line604 to supply a second signal having the first frequency and a constantphase offset with respect to the first signal. The frequency source 600may typically be a crystal oscillator (XO) or a microelectromechanicalsystem (MEMS) oscillator, but the system is not limited to anyparticular type of frequency source.

A multiplexer (MUX) 610 has inputs connected to the first and secondoutputs of the frequency source, respectively, on lines 602 and 604. TheMUX 610 has an output on line 204 to supply the analog reference signalin response to the maximum slope control signal on line 608 received ata control port. A slope detector 606 has an input on line 204 to samplethe first signal over a plurality of first signal periods and the secondsignal over a plurality of second signal periods. The slope detector 606compares the collected samples of the slope of the first signal to thecollected samples of the slope of the second signal and determines thesignal having the greater slope at a plurality of period referencepoints. The slope detector 606 supplies a maximum slope control signalat an output on line 608 in response to the comparison of the first andsecond signal slopes. For example, if the analog reference signal hasfour period reference points, the MUX 610 may select the first and thirdsamples from the first signal and second and fourth samples from thesecond signal as the supplied analog reference signal on line 204. Oncecollected by the slope detector 606, this slope comparison data may bestored in memory (not shown). The slope detector 606 may be clocked ortriggered using the system clock on line 206, but alternatively, othertrigger sources may be used. In other aspects not shown, the greatestslope from more than two input signals can be used as the analogreference signal.

Returning the FIG. 3, the jitter estimation module 214 further comprisesa first memory 306 to supply the ideal digitized reference signal online 308 from storage. A first subtractor 310 has an input on line 308to accept the ideal digitized reference signal from the first memory306, an input on line 212 to accept the digitized reference signal, andan output on line 312 to supply a difference signal. A second memory 314supplies the inverse of the derivative of the ideal digitized referencesignal from storage on line 316. The operation of taking the derivationof the ideal digitized reference signal is performed by derivative block318, and the operation of taking the inverse of the derivative isperformed by inverse block 320. These operations may be performed by thejitter estimation module 214 (as shown), or optionally, by a processorlocated outside the jitter estimation module, or even by a processoroutside the frequency multiplier jitter correction system. It shouldalso be noted that the operations of finding the ideal digitizedreference signal and the inverse derivative of the ideal digitizedreference signal may only be performed upon initial calibration orperiodically, permitting these results to be stored in memory. Moretypically, the ideal digitized reference signal is continuously updatedto cancel any drift in the analog reference signal, even if the drift isnot large enough to have a significant effect on the derivative.

A first multiplier 322 has an input on line 312 to accept the differencesignal, an input to accept the inverse of the derivative of the idealdigitized reference signal from the second memory on line 316, and anoutput to supply the phase error correction. In one aspect, the jitterestimation module 214 further comprises a low-pass filter (LPF) 324having an input connected to the output of the first multiplier 322 andan output on line 216 to supply a phase error correction that has beenfiltered. The low-pass filter 324 may be enabled as a finite impulseresponse (FIR) filter, but the system is not limited to any particularmeans of low-pass filtering.

FIG. 7 is a block diagram depicting the jitter correction module ingreater detail. In this aspect the jitter correction module 400 furthercomprises a derivative module 700 comprising a derivative filter 701.When the analog data signal is within the first Nyquist zone, thederivative filter 701 accepts the delayed digitized data signal at aninput on line 412 and supplies a derivative of the delayed digitizeddata signal on line 712. The analog data signal is in the first Nyquistzone if it has a frequency of less than one-half the frequency of thesystem clock by which it is being sampled. Alternatively stated, if thesystem clock frequency is f_(s), the first Nyquist zone is the band ofanalog data signal frequencies between 0 and f_(s)/2. A secondmultiplier 714 has an input on line 712 to accept the derivative of thedelayed digitized data signal, an input to accept the phase errorcorrection on line 216, and an output to supply a product on line 716. Asecond subtractor 718 has an input to accept the delayed digitized datasignal on line 412, an input on line 716 to accept the product forsubtraction from the delayed digitized data signal, and an output online 408 to supply the phase corrected digitized data signal.

FIG. 8 is a schematic block diagram of the derivative module of FIG. 7in the case where the analog data signal is outside of the first Nyquistzone, with a frequency of greater than f_(s)/2. In this case, thederivative filter 701 accepts the delayed digitized data signal on line412 and supplies a first result on line 802. A Hilbert transformer 804has an input to accept the delayed digitized data signal on line 412 andan output on line 806 to supply a second result. The Hilbert transformerchanges the phase of the input signal by 90 degrees. Both the derivativefilter 701 and Hilbert transformer 804 may be enabled as FIR filters, aswould be familiar to those skilled in the art of digital signalprocessing. However, the system is not limited to any particular meansof taking a derivative or changing the phase of a signal. A thirdmultiplier 808 has an input on line 806 to accept the second result, aninput on line 810 to accept a Nyquist zone-dependent constant, and anoutput on line 812 to supply a third result. A summing circuit 814 hasan input on line 802 to accept the first result, an input on line 812 toaccept the third result, and an output on line 702 to supply thederivative of the delayed digitized data signal. The Nyquistzone-dependent constant may be described as: (−1)^(k)└k/2┘π, whereinteger k represents the Nyquist zone (1 for the first zone, 2 for thesecond zone, and so on) and the brackets (└ ┘) denote rounding towardszero.

The above-described elements of the jitter estimation and jittercorrection modules may be enabled in hardware using complementary andhardwired state machine logic, in software using a processor enacting asequence of instructions stored in a non-transitory memory, or with acombination of hardware and software using a field programmable gatearray (FPGA) for example.

FIG. 9 is a schematic block diagram of a computer that may be used toenable all or some portions of ADCs, jitter estimation module, andjitter correction module. The computer 900 comprises a processor 902connected to a non-transitory memory 904 via data/address bus 906. Forthe sake of simplicity, the bus 906 is shown connected to the first ADC208, second ADC 404, jitter estimation module 214, and jitter correctionmodule 400 via an input/output (IO) interface 908. The IO interface 908may be enabled using one or more communication protocols known in theart. The memory 904 includes a first ADC application 910, a second ADCapplication 912, a jitter estimation application 914, and a jittercorrection application 916. The applications are sequences of softwareinstructions that are enacted by the processor 902 to perform variousfunctions. The memory may also include the first memory 306 and secondmemory 314 associated with the jitter estimation module. For example,the first and second ADC applications 910/912 may include instructionsfor an ADC that performs oversampling or interleaving. The jitterestimation application 914 may perform functions associated with thelow-pass filter and low-pass filter bank, first subtractor, and firstmultiplier, as well as functions associated with the derivative andinverse blocks. Likewise, the jitter correction module 916 may performfunctions associated with the delay, derivative filter, secondmultiplier, third multiplier, summing circuit, and second subtractor.

FIG. 10 depicts the system of FIG. 4 from a slightly differentperspective. The above-described system is based on the fact that if thereference comparison can be performed more often, ideally at everyoutput clock period, the phase error can be better corrected. In a PLLusing a digitized reference signal on line 1002, this is even moredifficult since the digitized reference signal is a two level signal andcontains phase information only at the transitions, twice in the clockperiod. However, a crystal oscillator 600 produces an analog referencefrequency on line 204 in nearly a sinusoidal form before it is squaredup and buffered by device 1000. Note: buffer device 1000 may be part ofa crystal oscillator having both an analog and digitized referencesignal output. A sinusoidal signal carries the phase information atevery time point, perhaps excluding the very peaks. Furthermore, if thephase correction can be applied in a feedforward rather than feedbackmanner, there are no stability constraints and a system using such phasecorrection information can respond much better to instantaneous phaseerrors.

The system uses an ADC 208 to sample the sinusoidal (or nearlysinusoidal) reference signal using the PLL output on line 206 as asampling (system) clock. A sampling clock without any phase noise wouldproduce a periodic ADC output signal that represents one period of thereference waveform. In the presence of PLL phase noise this same idealcurve can be estimated by averaging the signal over many referenceperiods. Now, every instantaneous sample of the reference clock can becompared to this nominal curve and the difference used to estimate thephase error in the PLL output. This estimate is in a digital form.

When a second ADC 404, which doesn't need to be identical, or even ofthe same type as the first ADC 208, is used to sample an analog inputsignal using the same PLL output as a sampling clock, the digital phaseerror estimate can be used to digitally correct the ADC 404 outputvalues. This correction is essentially a feedforward mechanism anddoesn't suffer from the stability constraints of a feedback system.

The first ADC 208 can operate at lower sampling rate than the second ADC404 and still provide close-in phase noise suppression. The phase errorestimates for the clock edges between the measured edges are based onnumerical interpolation, or alternatively, the previous estimate is usedfor all following edges until a new estimate is available.

To improve the phase estimation at the peaks of the reference waveform,a crystal oscillator circuit with two out-of-phase (e.g. sine andcosine) output signals can be used, see FIG. 6. With a dynamicallycontrolled MUX before the first ADC 208 (as shown in FIG. 6), or with anadditional ADC and digital MUX after the first ADC (not shown), thewaveform that has steeper slope can be selected for use as the analogreference signal.

FIGS. 11 and 12 are, respectively, an exemplary block diagram of thejitter estimation module, and associated waveforms. Samples out of thefirst ADC 208 are demultiplexed into n parallel streams by thedemultiplexer (DEMUX) 1100 of filter bank 300, each one representing onefixed point in the digitized reference waveform. The DEMUX 1100 iscontrolled by signals from a 1-to-n counter 1104, which is triggered bythe system clock on line 206. In an ideal case the values would beconstants, but in the presence of jitter in the system clock, and noisein the first ADC 208 and the oscillator 600, they are noisy. Toestablish the estimates of the ideal values, the data streams arefiltered by a low-pass filter 1102, which is implemented with n parallelfilters or with one filter that is time shared between n signal paths.The outputs of low-pass filter 1002 form the look-up-table (LUT) valuesin the first memory 306. These values are further used to build up asecond lookup table in the second memory 314 consisting of the inverseof the derivate of the reference waveform at each sample point.

To generate the jitter estimate for each system clock edge, the expectedreference waveform value, which is stored in the first lookup table 306,is first subtracted from the actual value sampled by the first ADC 208(the digitized reference signal on line 212). This signal represents thedifference between the ideal value and the actual one in the analogdomain. Assuming that all of the difference is due to clock jitter, thejitter estimate can be obtained by dividing the difference value by theslope of the waveform, which is equivalent to multiplying it by theinverse of the derivative that is stored in the second lookup table inthe second memory 314. Since the actual measurement contains someamplitude noise as well, the final output may be low-pass filtered byLPF 324 to give a better estimate of the close-in phase noise.Alternatively, the filtering can be performed with a band-pass filterbefore the first multiplier (not shown).

FIG. 13 depicts an example of the jitter correction module. Here, thesecond ADC 404, which uses the same PLL system clock as the jitterestimation (first) ADC, samples an arbitrary analog data waveform. Afterthe second ADC 404, the digitized data signal is delayed to properlyalign it with the jitter estimate (phase error correction). Thecorrection is accomplished by multiplying the estimate of the derivativeof the ADC input signal by the jitter estimate (phase error correction),and subtracting the result from the delayed digitized data signal. Ifthe analog data input signal on line 406 is in the first Nyquist zone,just the derivative filter 701 can be used to generate the estimate ofthe derivative. When the analog data signal is in other Nyquist zones,the sampling causes aliasing and the derivative obtained with aderivative filter in the digital domain is no longer a good estimate ofthe derivative of the analog signal. A proper estimate can be obtainedwith a combination of the derivative filter 701 and a Hilberttransformer 804 as shown in the figure. Additional details of theabove-described derivative module 700 can be found in parent applicationSer. No. 13/603,495, which is incorporated herein by reference.

Although many of the figures depict the frequency multiplier enabled asa PLL, it can also be based on a DLL for instance, and more generally,any other type of frequency multiplier.

FIG. 14 is a schematic block diagram depicting a variation of the phaseerror correction system. In this system, two ADCs 1402 and 1404 samplethe same analog input signal on line 1406. The main ADC 1404 is clockedwith from PLL 1414 with a PLL clock on line 1408 and the second ADC 1402with a crystal oscillator 1410 on line 1412. The PLL clock rate is Ntimes the crystal oscillator reference signal frequency. The crystaloscillator reference signal has very little phase noise, and as aresult, the digital samples out of the second ADC 1402 on line 1418 havevery little error due to clock jitter. The PLL clock on line 1408suffers from close-in phase noise which causes error in the data comingout of the main ADC 1404 on line 1416. Using the under-sampled cleandata from the second ADC 1402 as a reference, the PLL clock jitter isestimated from the output of the main ADC 1404 and used to digitallycorrect the data by jitter detection and correction block 1420.

FIG. 15 is a schematic block diagram depicting an exemplary jitterdetection and correction module, such as might be used in the system ofFIG. 14. First, the main ADC 1404 sampled data is aligned with thesecond ADC 1402 sampled data by adjusting its amplitude and offset atblock 1500, and delay at block 1502, using data alignment control block1504. The delay adjustment can be done by adjusting the delay of theXTAL reference clock (line 1412) in the analog domain (not shown) or byadjusting the delay of the PLL clock in the analog domain at block 1506.Alternatively as shown, the delay adjustment is performed digitallyusing fractional delay filter 1502 or done using extrapolation with theaid of the derivative of the signal (not shown).

Next, the reference signal from ADC 1402 is subtracted from the alignedoutput of the main ADC 1404 by subtractor 1510 to form the error signalon line 1508. The error signal is divided by the inverse derivative ofthe analog input signal, using blocks 1512 and 1514, and low-passfiltered by block 1516 to get the jitter estimate on line 1518. Thejitter estimate is updated every Nth clock of the main ADC 1404 andinterpolation is used to obtain the values in between. The phasecorrection is identical to the one described above in the explanationsof FIGS. 7 and 8. That is, the digitized data signal form ADC 1404 iscorrected by multiplying the jitter estimate (phase error correction) bythe derivative using multiplier 1520 to obtain the product on line 1522,and subtracting the product from the delayed digitized data signal online 1524 at subtractor 1526 to obtain phase corrected digitized datasignals.

Although not explicitly shown, the system of FIG. 14 may be implementedusing a frequency source other than a crystal oscillator and a frequencymultiplier other than a PLL. Further, the elements depicted in FIGS. 14and 15 may be enabled in hardware, software, or with a combination ofhardware and software.

FIGS. 17A and 17B are schematic block diagrams of a system forcorrecting the phase error in the system clock signal. In these examplesthe analog reference signal is supplied by crystal oscillator 1702 andthe frequency multiplier 202 is a PLL, but the systems are not limitedto any particular type of frequency source or frequency multiplier. InFIG. 17A, a programmable delay 1700 has an input to accept the systemclock signal on line 206 and an input on line 216 to accept the phaseerror correction. The programmable delay 1700 has a programmable delayresponsive to the phase error correction, and an output on line 1704 tosupply a phase corrected system clock signal. FIG. 17B is the same as17A, except the system clock signal accepted by the first ADC 208 is thephase corrected system clock signal on line 1704. Note: when applyingthe phase error correction to the system clock signal, the correction isalways late due to jitter estimation module processing, limiting thecorrection bandwidth that is possible. Having an ADC with a low latencyand calculating the phase error correction using a minimum number ofclock cycles can minimize this penalty. In contrast, the application ofa feedforward phase error correction to the digitized data signal doesnot suffer from this limitation.

FIG. 18 is a schematic block diagram depicting an alternate system forcorrecting system clock signal phase error. In this system the systemclock signal is the same as the phase corrected system clock signal.Again in this example the analog reference signal is supplied by crystaloscillator 1702 and the frequency multiplier 202 is a PLL, but thesystem is not limited to any particular type of frequency source orfrequency multiplier. The clock input of the first ADC 208 accepts thephase corrected system clock signal on line 1704. The frequencymultiplier has an input to accept the phase error correction on line 216and an output to supply the phase corrected system clock signal on line1704.

FIGS. 19A and 19B are schematic block diagrams depicting two examples ofthe system of FIG. 18 in greater detail. In short, the frequencymultiplier (PLL) 202 comprises a system clock oscillator 1900 to createthe phase corrected system clock signal on line 1704 in response to acombination of control signals derived from the phase error correctionon line 216, system clock oscillator negative feedback on line 1902, andthe analog reference signal on line 204, which is digitized on line1002. Both examples include a digital loop filter 1904, a phasefrequency detector (PFD) 1906, loop divider 1908, and post dividers 1910and 1912. Post dividers 1910 and 1912 permit the generation of a PLLclock signal on line 1914 that has a different frequency that the phasecorrected system clock signal on line 1704.

In FIG. 19A, the system clock oscillator 1900 is a digitally controlledoscillator (DCO), and summing device 1916 combines digital controlsignals from digital loop filter 1904 and digital loop filter 1916.Note: the digital control signal output by digital loop filter 1916 isresponsive to the analog reference signal on line 204 and negativefeedback on line 1902.

In FIG. 19B, the system clock oscillator 1900 is a controlled oscillator(CO) having a digital input (D) to accept a digital control signal fromdigital loop filter 1904 and an analog input (A) to accept an analogcontrol signal from analog loop filter 1918. The analog control signalsupplied by analog loop filter 918 is responsive to the analog referencesignal on line 204 and negative feedback on line 1902.

FIGS. 16A and 16B are flowcharts illustrating a method for frequencymultiplication jitter correction. Although the method is depicted as asequence of numbered steps for clarity, the numbering does notnecessarily dictate the order of the steps. It should be understood thatsome of these steps may be skipped, performed in parallel, or performedwithout the requirement of maintaining a strict order of sequence.Generally however, the method follows the numeric order of the depictedsteps. The method starts at Step 1600.

Step 1602 accepts an analog reference signal having a first frequency.Using the analog reference signal, Step 1604 derives a system clocksignal having a second frequency, greater than the first frequency. Step1606 samples the amplitude of the analog reference signal using thesystem clock signal. Step 1608 converts the sampled analog referencesignal into a digitized reference signal. In one aspect, Step 1610 acollects samples of the digitized reference signal over a plurality ofdigitized reference signal periods, at a plurality period referencepoints, and Step 1610 b low-pass filters the collected samples of thedigitized reference signal period reference point samples to create anideal digitized reference signal. Step 1612 compares the digitizedreference signal to the ideal digitized reference signal. In response tothe comparing, Step 1614 derives a phase error correction for the systemclock signal.

In one aspect, Step 1614 derives a phase error correction at a firstinstance of time. Step 1616 accepts an analog data signal at the firstinstance of time. Step 1618 samples the amplitude of the analog datasignal with a system clock signal. Step 1620 converts the sampled analogdata signal into a digitized data signal. Step 1622 applies the phaseerror correction to the digitized data signal.

In one aspect, the determining of the phase error in Step 1612 and theapplying of the phase error correction in Step 1622 occur over aduration of time no greater than a first duration of time. Then, Step1622 comprises the following substeps. Step 1622 a delays the digitizeddata signal the first duration of time to supply a delayed digitizeddata signal. Step 1622 c applies the phase error correction to thedelayed digitized data signal.

In another aspect, using the analog reference signal to derive thesystem clock signal having the second frequency in Step 1604additionally includes using the analog reference signal to derive asystem clock signal having a third frequency, different than the firstand second frequencies. Then, sampling the analog reference signal usingthe system clock signal in Step 1606 includes sampling the analogreference signal with the system clock signal having the secondfrequency. Sampling the analog data signal with the system clock in Step1618 includes sampling the analog data signal with the system clocksignal having the third frequency.

In one aspect, Step 1601 a generates a first input signal having thefirst frequency, and a second input signal having the first frequencyand a constant phase offset with respect to the first input signal. Step1601 b compares the slope of the first input signal to the slope of thesecond input signal. Step 1601 c determines the input signal having thegreater slope. Then, accepting the analog reference signal in Step 1602includes accepting the input signal having the greater slope as theanalog reference signal.

In another aspect, comparing the digitized reference signal to the idealdigitized reference signal in Step 1612 includes subtracting the idealdigitized reference signal from the digitized reference signal to supplya difference signal. Then, deriving the phase error correction in Step1614 comprises the following substeps. Step 1614 a finds the inverse ofthe derivative of the ideal digitized reference signal. Step 1614 bmultiplies the difference signal by the inverse of the derivative.Alternatively stated, Step 1614 b divides the difference signal by thederivative of the ideal digitized reference signal. In one variation,Step 1614 c performs a low-pass filtering operation subsequent to Step1614 b.

In one aspect, applying the phase error correction to the delayeddigitized data signal comprises the following additional substeps. Whenthe analog data signal is inside the first Nyquist zone, Step 1622 bfinds the derivative of the delayed digitized data signal. Step 1622 cmultiplies the derivative of the delayed digitized data signal by thephase error correction to supply a product. Step 1622 d subtracts theproduct from the delayed digitized data signal. When the analog datasignal is outside of the first Nyquist zone, Step 1622 b finds thederivative of the delayed digitized data signal to supply a firstresult. Step 1622 b 1 performs a Hilbert transformation on the delayeddigitized data signal to supply a second result. Step 1622 b 2multiplies the second result by a Nyquist zone-dependent constant tosupply a third result. Step 1622 b 3 sums the first result with thethird result to supply the product.

In one aspect, Step 1624 delays the system clock signal a duration oftime equal to a programmable delay responsive to the phase errorcorrection. Step 1626 creates a phase corrected system clock signal. Inone variation, Step 1606 samples the amplitude of the analog referencesignal using a phase corrected system clock signal instead of with thesystem clock signal.

In another aspect, Step 1606 samples the amplitude of the analogreference signal using a phase corrected system clock, and Step 1604derives the system clock with the following substeps. Step 1604 acontrols a system clock oscillator in response to a combination ofcontrol signals derived from system clock oscillator negative feedback,the analog reference signal, and the phase error correction. Step 1604 bcreates the phase corrected system clock signal.

A system and method have been provided for the correction of frequencymultiplier phase errors. Particular process steps and hardware circuitshave been presented as examples to explain the system and methods, butthe systems and methods are not necessarily limited by these examples.Further, although crystal oscillators and PLLs have been explicitlydepicted as examples of, respectively, a frequency source and afrequency multiplier, the systems and methods are not limited to theseexamples. Other variations and modifications of the above-describedsystems and methods will likely occur to those skilled in the art.

We claim:
 1. A method for adjusting a system clock to correct for clockjitter, the method comprising: accepting an analog reference signal;sampling an amplitude of the analog reference signal using a firstsystem clock signal having a first frequency, derived from the analogreference signal; in response to the sampling, supplying a firstreference digitized signal; deriving phase error corrections for thefirst reference digitized signal; applying the phase error correctionsto the system clock signal by programmably delaying the first systemclock signal in response to the phase error corrections; and, supplyinga phase corrected second system clock signal as a result of programmablydelaying the first system clock signal. 2-8. (canceled)
 9. The method ofclaim 1 wherein deriving phase error corrections for the first referencedigitized signal includes: collecting samples of the first referencedigitized signal over a plurality of first reference digitized signalperiods, at a plurality period reference points; low-pass filtering thecollected samples of the first reference digitized signal, to create anideal first reference digitized signal; subtracting the ideal firstreference digitized signal from the first reference digitized signal tosupply a difference signal; finding an inverse of a derivative of theideal digitized reference signal; and, multiplying the difference signalby the inverse of the derivative.
 10. The method of claim 1 whereinaccepting the analog reference signal includes accepting an analogreference signal having a third frequency, less than the firstfrequency.
 11. A system for adjusting a system clock to correct forclock jitter, the system comprising: a frequency source having an outputto supply an analog reference signal; an analog-to-digital converter(ADC) having an input to accept the analog reference signal, a clockinput to accept a system clock signal having a first frequency, and anoutput to supply a first reference digitized signal; a frequencymultiplier having an input to accept the analog reference signal and anoutput to supply a first system clock signal; a jitter estimation modulehaving an input to accept the first reference digitized signal, and anoutput to supply phase error corrections; a programmable delay having aninput to accept the first system clock, an input to accept the phaseerror corrections, and an output to supply a phase corrected secondsystem clock signal.
 12. The system of claim 11 wherein ADC clock inputaccepts a system clock selected from a group consisting of the firstsystem clock and the second system clock.
 13. The system of claim 11wherein the jitter estimation module comprises: a low-pass filter bankwith an input to accept the first reference digitized reference signal,the low-pass filter bank sampling the first reference digitizedreference signal over a plurality of first reference digitized signalperiods, at a plurality of period reference points, and supplying anideal first reference digitized signal at an output, a first memory tosupply the ideal first reference digitized signal from storage; a firstsubtractor having an input to accept the ideal first reference digitizedsignal from the first memory, an input to accept the first referencedigitized signal, and an output to supply a difference signal; a secondmemory to supply an inverse of a derivative of the ideal first referencedigitized signal from storage; and, a first multiplier with an input toaccept the difference signal, an input to accept the inverse of thederivative of the ideal first reference digitized signal from the secondmemory, and an output to supply the phase error corrections.
 14. Thesystem of claim 11 wherein the frequency source supplies an analogreference signal having a third frequency, less than the firstfrequency.
 15. A system for adjusting a system clock to correct forclock jitter, the system comprising: a frequency source having an outputto supply an analog reference signal; an analog-to-digital converter(ADC) having an input to accept the analog reference signal, a clockinput to accept a phase corrected system clock signal having a firstfrequency, and an output to supply a first reference digitized signal; ajitter estimation module having an input to accept the first referencedigitized signal, and an output to supply phase error corrections; afrequency multiplier having an input to accept the analog referencesignal, an input to accept the phase error corrections, and an output tosupply the phase corrected system clock signal; wherein the jitterestimation module comprises: a low-pass filter bank with an input toaccept the first reference digitized reference signal, the low-passfilter bank sampling the first reference digitized reference signal overa plurality of first reference digitized signal periods, at a pluralityof period reference points, and supplying an ideal first referencedigitized signal at an output; a first memory to supply the ideal firstreference digitized signal from storage; a first subtractor having aninput to accept the ideal first reference digitized signal from thefirst memory, an input to accept the first reference digitized signal,and an output to supply a difference signal; a second memory to supplyan inverse of a derivative of the ideal first reference digitized signalfrom storage; and, a first multiplier with an input to accept thedifference signal, an input to accept the inverse of the derivative ofthe ideal first reference digitized signal from the second memory, andan output to supply the phase error corrections.
 16. The system of claim15 wherein the frequency multiplier is a phase-locked loop (PLL)comprising: a phase frequency detector (PFD) having an input to acceptthe analog reference signal, an input to accept a synthesized signal asnegative feedback, and an output to supply a digital control signal; asumming circuit having an input to accept the control signal, an inputto accept digital phase error corrections, and an output to supply adigital sum; and, a digitally controlled oscillator (DCO) having aninput to accept the digital sum and an output to supply the synthesizedsignal.
 17. The system of claim 15 further comprising: a first postdivider to accept the synthesized signal and an output to supply thephase corrected system clock signal; and, a second post divider toaccept the synthesized signal and an output to supply an auxiliary phasecorrected system clock signal having a second frequency, different thanthe first frequency.
 18. The system of claim 15 wherein the frequencymultiplier is a PLL comprising: a PFD having an input to accept theanalog reference signal, an input to accept a synthesized signal asnegative feedback, and an output to supply an analog control signal;and, a controlled oscillator (CO) having an input to accept digitalphase error corrections, an input to accept the analog control signal,and an output to supply the synthesized signal.
 19. (canceled)
 20. Thesystem of claim 15 wherein the frequency source supplies an analogreference signal having a third frequency, less than the firstfrequency.
 21. A method for adjusting a system clock to correct forclock jitter, the method comprising: accepting an analog referencesignal; sampling an amplitude of the analog reference signal using asecond system clock signal having a first frequency, derived from theanalog reference signal; in response to the sampling, supplying a firstreference digitized signal; deriving phase error corrections for thefirst reference digitized signal; applying the phase error correctionsto the system clock signal by programmably delaying a first system clocksignal in response to the phase error corrections; and, supplying thesecond system clock as a result of programmably delaying the firstsystem clock signal.
 22. The method of claim 21 wherein deriving phaseerror corrections for the first reference digitized signal includes:collecting samples of the first reference digitized signal over aplurality of first reference digitized signal periods, at a pluralityperiod reference points; low-pass filtering the collected samples of thefirst reference digitized signal, to create an ideal first referencedigitized signal; subtracting the ideal first reference digitized signalfrom the first reference digitized signal to supply a difference signal;finding an inverse of a derivative of the ideal digitized referencesignal; and, multiplying the difference signal by the inverse of thederivative.
 23. A method for adjusting a system clock to correct forclock jitter, the method comprising: accepting an analog referencesignal; sampling an amplitude of the analog reference signal using asystem clock signal having a first frequency, derived from the analogreference signal; in response to the sampling, supplying a firstreference digitized signal; deriving phase error corrections for thefirst reference digitized signal; applying the phase error correctionsto a phase-locked loop (PLL) having an input to accept the analogreference signal, an input to accept the phase error corrections, and anoutput to supply the phase corrected system clock signal, as follows:detecting phase differences between the analog reference signal and anegative feedback synthesized signal, to supply a control signal;summing the control signal with the phase error corrections to supply asum; and, generating the phase corrected system clock signal in responseto sum as follows: dividing the synthesized signal by a first postdivider to supply the phase corrected system clock signal; and, dividingthe synthesized signal by a second post divider to supply an auxiliaryphase corrected system clock signal having a second frequency, differentthan the first frequency.
 24. The method of claim 23 wherein derivingphase error corrections for the first reference digitized signalincludes: collecting samples of the first reference digitized signalover a plurality of first reference digitized signal periods, at aplurality period reference points; low-pass filtering the collectedsamples of the first reference digitized signal, to create an idealfirst reference digitized signal; subtracting the ideal first referencedigitized signal from the first reference digitized signal to supply adifference signal; finding an inverse of a derivative of the idealdigitized reference signal; and, multiplying the difference signal bythe inverse of the derivative.
 25. A method for adjusting a system clockto correct for clock jitter, the method comprising: accepting an analogreference signal; sampling an amplitude of the analog reference signalusing a system clock signal having a first frequency, derived from theanalog reference signal; in response to the sampling, supplying a firstreference digitized signal; deriving phase error corrections for thefirst reference digitized signal as follows: collecting samples of thefirst reference digitized signal over a plurality of first referencedigitized signal periods, at a plurality period reference points;low-pass filtering the collected samples of the first referencedigitized signal, to create an ideal first reference digitized signal;subtracting the ideal first reference digitized signal from the firstreference digitized signal to supply a difference signal; finding aninverse of a derivative of the ideal digitized reference signal;multiplying the difference signal by the inverse of the derivative;applying the phase error corrections to the system clock signal; and,supplying a phase corrected system clock signal.
 26. The method of claim25 wherein applying the phase error corrections to the system clocksignal includes applying the phase error corrections to a frequencymultiplier having an input to accept the analog reference signal, aninput to accept the phase error corrections, and an output to supply thephase corrected system clock signal.
 27. The method of claim 25 whereinaccepting the analog reference signal includes accepting an analogreference signal having a third frequency, less than the firstfrequency.
 28. A system for adjusting a system clock to correct forclock jitter, the system comprising: a frequency source having an outputto supply an analog reference signal; an analog-to-digital converter(ADC) having an input to accept the analog reference signal, a clockinput to accept a phase corrected system clock signal having a firstfrequency, and an output to supply a first reference digitized signal; ajitter estimation module having an input to accept the first referencedigitized signal, and an output to supply phase error corrections; afrequency multiplier having an input to accept the analog referencesignal, an input to accept the phase error corrections, and an output tosupply the phase corrected system clock signal; a first post divider toaccept the synthesized signal and an output to supply the phasecorrected system clock signal; and, a second post divider to accept thesynthesized signal and an output to supply an auxiliary phase correctedsystem clock signal having a second frequency, different than the firstfrequency.